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NCP3011, NCV3011
Reduced sampling time occurs at high duty cycles where
the low side MOSFET is off for the majority of the switching
period. Reduced sampling time causes errors in the
regulated voltage on the boost pin. High duty cycle / input
voltage induced sampling errors can result in increased
boost ripple voltage or higher than desired DC boost voltage.
Figure 39 outlines all operating regions.
The recommended operating conditions are shown in
Region 1 (Green) where a 0.1 m F, 25 V ceramic capacitor
can be placed on the boost pin without causing damage to the
device or MOSFETS. Larger boost ripple voltage occurring
The boost ripple frequency is dependent on the output
capacitance selected. The ripple voltage will not damage the
device or $ 12 V gate rated MOSFETs.
Conditions where maximum boost ripple voltage could
damage the device or $ 12 V gate rated MOSFETs can be
seen in Region 3 (Orange). Placing a boost capacitor that is
no greater than 10X the input capacitance of the high side
MOSFET on the boost pin limits the maximum boost
voltage < 12 V. The typical drive waveforms for Regions 1,
2 and 3 (green, yellow, and orange) regions of Figure 39 are
shown in Figure 40.
over several switching cycles is shown in Region 2 (Yellow).
Boost Voltage Levels
Normal Operation
Increased Boost Ripple
(Still in Specification)
Increased Boost Ripple
Capacitor Optimization
Required
28
26
24
22
20
22V
Region 3
18
16
14
Region 1
Region 2
Max
Maxi
mum
Duty
Cycle
12
10
8
6
4
11.5V
71%
2
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
Duty Cycle
Figure 39. Safe Operating Area for Boost Voltage with a 0.1 m F Capacitor
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